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Functional-Verification Heavyweight Raises Scalability The electronic-design-automation (EDA) industry seeks to provide a crystal ball of sorts. Using EDA tools, designers and architects can predict many aspects of a chip's performance. When it comes to functional verification, however, the answers get... — Nancy Friedrich February 2004 [Column] Verification Tools Expand To Cover The ESL Space The need for verification has become a driving force behind the resurgence of electronic-system-level (ESL) development tools. Previously, ESL tools claimed to enable accurate chip design above the register-transfer level (RTL). Today, however,... — John Blyler February 2004 [Show Coverage] Electromagnetic Software Eases Design The successful analysis of high-frequency electromagnetic (EM) circuits is critical to a whole host of wireless applications. Such analysis is needed for the design of microstrip and stripline circuits, planar spiral inductors, RFIC and MMIC... — John Blyler February 2004 [New Products] Mobile-Design Solution Fills Development Needs It seems that the creation of mobile-computing devices may have just gotten easier. In part, the credit for this improvement should go to the new Metrowerks OpenPDA platform and CodeWarrior for OpenPDA Application Development Tools. The OpenPDA... — Nancy Friedrich November/December 2003 [Product Features] Design-For-Test System Fits Desktop Wireless designers are very well acquainted with time-to-market pressures. In hopes of escaping this familiar tension, they warmly welcome anything that can reduce these pressures—especially if it also lowers product-development costs. Among the... — John Blyler November/December 2003 [Product Features] C Synthesis Nurtures FPGA Development The design starts that use reconfigurable processors—namely field-programmable gate arrays (FPGAs)—continue to grow in popularity. In fact, a recent Gartner Dataquest study found that FPGAs and application-specific signal processors (ASSPs)... — John Blyler October 2003 [Special Section] Co-Existence Warrants A Second Glance After another long and productive circuit-simulation session, Joe Engineer needed a break. "To reward myself, I'll download the complete works of Britney Spears MPEG collection," thought Joe. He figured that transferring the several-hundred-megabyte... — Afshin Amini , et al. October 2003 [Product Features] Coprocessor Synthesis Offloads Software Tasks For experienced wireless designers, the migration path from software to hardware is a familiar one. After all, newer technologies are first implemented in software to gain efficiency and expediency. Examples include Java, multimedia (MPEG-4), and 3G... — John Blyler October 2003 [Product Features] Test-Vector Generation Draws Major Gains To design complex ASICs in a timely and cost-effective manner, engineers must incorporate various design-for-test (DFT) methodologies. Early on, for example, they must add boundary as well as internal built-in self-test (BIST) structures and scan... — John Blyler September 2003 [Design Application] System Verification Comes To SystemC It is widely accepted that system verification is the most imposing obstacle to meeting time-to-market schedules. Now, the verification process has become even more time-consuming and expensive. These factors can be attributed to rising chip... — Adam Rose September 2003 [Design Application] Analyze And Optimize Throughout The Flow The increased use of portable, wireless, battery-powered electronic systems is driving the demand for integrated-circuit (IC) and system-on-a-chip (SoC) devices. After all, these devices consume the smallest possible amounts of power. With every new... — Sameer Patel July/August 2003 [Product Features] FPGA Tool Beckons DSP Designers Most analysts agree that this year, the growth rates of field-programmable gate arrays (FPGAs) will actually double that of application-specific integrated circuits (ASICs). Of course, FPGAs have been gaining market traction for some time. Seeing... — John Blyler July/August 2003 [Product Features] ASIC Designers See Software's Potential Several factors are blurring the line between ASICs and FPGAs. From design flows and performance to high-volume production rates, FPGAs are looking more and more like ASICs. This transformation is being helped by Altera Corp.'s recent introduction... — John Blyler July/August 2003 [New Products] Easily Prototype Large Antennas And Backplanes Printed-circuit-board (PCB) designs have become as complex as their ASIC and ASSP counterparts. This is especially true in wireless systems—mainly because of the analog and radio-frequency elements. In an effort to simplify matters, T-Tech has... — Staff July/August 2003 [News] Duo Expedites Prototyping And Verification Recently, quite a few companies have teamed up to quicken the radio-frequency design flow. An example is the recent partnering of National Instruments (http://ni.com) and Ansoft Corp. (www.ansoft.com). These companies have merged the Ansoft Designer... — Nancy Konish July/August 2003 [Column] What Was The Essence Of DAC '03? When you write about technology on a full-time basis, it's sometimes difficult to keep a clear and unbiased perspective. This is hardly surprising, as most editors are inundated with pitches from companies that are trying to put their best foot... — John Blyler June 2003 [Show Coverage] Realize The Wireless Connectivity Vision Wireless connectivity continues to grow. It promises to eradicate the information barriers of the wired world. Yet a big gap still exists between today's wireless technology and tomorrow's vision of ubiquitous information that's available anytime,... — Sharad Malik June 2003 [New Products] Stacked-Die Package Design Gets Easier One of Cadence's big announcements at DAC concerned a new auto-wirebond capability for designing stacked-die packages. For space-constrained cell phones and wireless handheld devices, reduced chip-size advantages can be gained from stacking die two,... — John Blyler June 2003 [New Products] Co-Verification Tool Gains Analysis One of the important elements of a system-level design methodology is the co-verification of both hardware and software subsystems. The goal of Mentor Graphics' latest version of Seamless is to address this challenge. This version even goes one step... — John Blyler June 2003 [New Products] Prediction Serves Low-Power RTL Designs Today's mobile wireless devices demand power-efficient systems. At the register transfer level (RTL), however, it is very difficult to accurately estimate power consumption and design for low power. The problem is that power usage depends on the... — John Blyler  prev. page
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