NAND is used for both code and data storage, while the low-power SDRAM is utilized for memory workspace. With the shadowing architecture, the code and data to be processed is loaded from NAND directly into SDRAM. This approach boasts significantly lower cost and faster speeds. Such functionality is beneficial to newer multimedia applications. The disadvantage is that it requires a major software change from the conventional approach. Often, this change translates into a longer development time for initial designs. But chip-set vendors are starting to support this feature in their products, so cell-phone designers don't need to worry about this too much.

Both memory architectures can be scaled to provide similar solutions with different memory densities. As a result, designers can easily create low-end, mid-range, and high-end variations of a basic phone design without having to make major changes to the memory subsystem. Different configurations of stacked MCPs also can be used as needed. They will support the features that are provided on different handset models.

To help designers evaluate the pros and cons of these memory architectures, let's take a more in-depth look at their performance characteristics and tradeoffs:

NOR Flash
Traditionally, NOR-Flash memory has been used for code storage in mobile phones. It offers fast random read speeds (typically 65 ns) and boot capability. It is designed to execute code directly out of memory.

The features of NOR Flash are well suited to the random-access requirements of code storage. This memory architecture achieves random access by connecting the memory cells to the bit lines in parallel. If any memory cell is turned on by the corresponding word line, the bit line goes low (FIG. 5). Because the logic function is similar to a NOR gate, this cell arrangement results in NOR Flash.

NOR-Flash densities haven't kept pace with the density requirements of cell phones, however. This architecture's relatively large cell size (10F², where F = design rule) has kept NOR Flash at a higher price than NAND Flash in cases of the same density. Existing MLC NOR Flash attempts to narrow this gap in cell size. But MLC NAND, which is in production now, appears to widen this gap. As a result, many cell phones continue to use the 32 to 128 Mb of NOR for the cell-phone operating-code storage. To support other functions, they turn to alternate types of memory.

The advantages of NOR Flash are defined by high-speed random access and the ability to program at the byte level. Its disadvantages include the slow programming of large data blocks and a slower erasing speed (typically 700 ms per block). By comparison, NAND has an erase speed of 2 ms per block (SEE TABLE).

NAND Flash
Initially, Toshiba Corp. developed NAND Flash as a solid-state replacement for magnetic memory. To keep the cost per bit as low as possible, NAND Flash features a much smaller cell size than either NOR Flash or other nonvolatile memory. The NAND-Flash cell contains an array with either 16 or 32 memory transistors in series. This cell array has one memory transistor and two select transistors per each NAND chain of cell. Every transistor in a NAND chain of cell can share each source or drain area and reduce the number of contacts. This technology realizes a small cell area without scaling down the device dimensions.

In a consumer-electronics application, one of the most important characteristics of memory is the bit cost. In the case of a semiconductor memory, the bit cost is dependent on the memory cell area per bit. The cell area of NAND Flash is much smaller than the cell area of NOR Flash. As a result, NAND Flash has the potential to be less expensive. In addition to the cost, NAND's smaller cell size enables very huge-density nonvolatile memory of 1 Gb and up.

Because of its low cost per bit and higher-density part availability, NAND Flash was initially an attractive addition to the cell-phone-memory subsystem. It was used to store additional programs and data. Now, multiple cell-phone chip sets include support for NAND Flash. Consequently, some cell-phone manufacturers are using a combination of NAND plus low-power SDRAM to handle all of the cell phone's memory requirements. Chip sets already are capable of booting up in the system using NAND Flash and SDRAM without NOR Flash.

Conventional NAND Flash requires the chip-enable signal to be asserted low during the entire read cycle. This move prevents the processor from communicating with other devices on the same bus. NAND Flash for cell phones has a feature called "Chip Enable Don't Care," which allows the chip-enable signal to be de-asserted during the read busy period. The microprocessor can then communicate with other memory devices on the same bus, such as SRAM, PSRAM, or NOR Flash without hardware changes.

Meanwhile, the NAND Flash retrieves the information that was requested. This feature allows the read command to continue even if the chip-enable signal is de-asserted. It also permits the processor to communicate with the I/O device during the read busy period.

Referring back to the table, the advantages of NAND include high-speed programming (write capability) and high-speed erasing. Unfortunately, NAND also has slower random access and no capability for byte-level programming. The access time for NAND is 50 ns for a typical serial-access cycle and 25 ms for an initial random-access cycle. Compare that number to 70 ns for a NOR-Flash random-access cycle. When huge data like a digital camera picture is read out, there is no significant difference between them. When a typical program and erase sequence is compared for NOR and NAND Flash using a 64-KB block, NAND outperforms NOR by a wide margin (33.6 ms for NAND compared to 1.23 sec./block for NOR).