Seoul, Korea
Samsung Electronics Co., Ltd. has developed an eight-die multi-chip-package (MCP) technology. This technology was designed for use in high-capacity mobile devices, such as third-generation (3G) handsets and other increasingly smaller mobile devices. Typically, as the number of chips per memory package increases, so does the thickness of the package. Using its Wafer Supporting System technology to makes wafers thinner during design processing, Samsung has been able to minimize overall chip thickness while decreasing the space between the stacked dies. As a result, the eight-die MCP solution offers a combined capacity of 3.2 Gb in a package that is 1.4 mm thick. It equals the thickness of a four-die MCP solution.

The new eight-chip multi-chip package is an extremely compact, high-capacity solution that is likely to trigger the development of new next-generation mobile applications. It will provide much greater functionality in cell phones and other smart mobile devices, which will range from movie videos to games and faster Internet access.

The eight-die MCP uses all of the memory chips available today for mobile products in a single 11-×-14-×-1.4-mm package. It includes two 1-Gb NAND Flash memories, two 256-Mb NOR Flash memories, two 256-Mb mobile DRAMs, one 128-Mb UtRAM, and one 64Mb UtRAM.

For more information, visit www.samsung.com.

San Jose, California
Recently, Altera Corp. and PMC-Sierra, Inc. announced a partnership to deliver a full suite of interoperable high-speed serial-I/O solutions based on Altera's programmable logic and PMC-Sierra's transceiver technologies. The combination of these technologies targets users of Altera's low-cost Cyclone II field-programmable-gate-array (FPGA) family, high-density Stratix II FPGA family, or HardCopy II structured-application-specific-integrated-circuit (ASIC) family. It will allow those users to seamlessly integrate these devices into systems based on high-speed serial protocols via PMC-Sierra's PM8358 QuadPHY 10GX serializer-deserializer (SERDES) transceiver. This new chip-set solution complements Altera's FPGAs with integrated transceivers and PMC Sierra's ASSPs. It also extends the options for customers targeting high-volume, cost-sensitive backplane and line-interface solutions.

Designers are increasingly using serial protocols including PCI Express, Advanced Switching, Serial RapidIO, Gigabit Ethernet, XAUI, Fibre Channel (1G, 2G, and 10G), Open Base Station Architecture Initiative (OBSAI), and Common Protocol Radio Interface (CPRI) to implement chip-to-chip, board-to-board, and system-to-system communication. The flexibility of PMC-Sierra's PM8358 transceiver, when combined with Altera FPGAs, allows customers using these protocols to design cost-sensitive and high-performance products. For those customers who prefer a single FPGA/transceiver solution, Altera offers integrated SERDES solutions.

A comprehensive package of design support materials including an evaluation board featuring the PMC-Sierra PM8358 transceiver and the Altera Stratix II EP2S90 device will be available in the second quarter of 2005.

For more information about PMC-Sierra's QuadPHY 10GX SERDES, visit www.pmc-sierra.com/serdes. To find out more about Altera, go to www.altera.com.

San Jose, California
Xilinx, Inc. announced production qualification of the first three devices in its 90-nm Virtex-4 field-programmable-gate-array (FPGA) family. With the qualification of the LX25, LX60, and SX35, Xilinx now has a total of 14 FPGAs in production at 90 nm—more than three times the number of its nearest competitor. The company leads the programmable-logic-device (PLD) industry by more than a year on 90-nm process technology. It has shipped over 1.5 million 90-nm devices.

Developed using a unique 90-nm, triple-oxide CMOS technology, the Xilinx Virtex-4 family provides the industry's highest performance. Logic, memory, clocking, and signal-processing blocks are tuned to 500-MHz performance while reducing power consumption to as little as a tenth the consumption of competing devices.

The Virtex-4 FPGAs are enabled by the Advanced Silicon Modular Block (ASMBL) architecture and advanced 90-nm triple-oxide technology. They claim to deliver more options, higher performance, and lower power than any other FPGA family available today. With more than 100 technical innovations, the Virtex-4 family consists of 17 devices and three domain-optimized platforms: Virtex-4 LX FPGAs optimized for logic-intensive designs; Virtex-4 SX FPGAs optimized for high-performance signal processing; and Virtex-4 FX FPGAs optimized for high-speed serial connectivity and embedded processing. A multi-platform approach makes it possible for customers to select the optimal mix of resources for their application to achieve the highest functionality and breakthrough performance at the lowest cost. Devices are shipping now.

For more information on the Virtex-4 product family, visit www.xilinx.com/virtex4.

Milpitas, California
Recently, Linear Technology released two radio-frequency active mixers that offer superior linearity while reducing power consumption. The LT5526 features an Input Third-Order Intercept (IIP3) of 16.5 dBm at 900 MHz and a noise figure of 11 dB. This performance is complemented by a conversion gain of 0.6 dB. Moreover, the LT5526 requires only −5 dBm LO drive. Its port-to-port LO leakage is very low at −65 dBm, reducing external filtering requirements. The LT5526 has fully differential inputs and outputs. It operates over a very wide bandwidth ranging from 100 kHz to 2 GHz. The device has the capability for use as either a downconverting mixer or as an upconverting mixer in many applications.

Its counterpart, the LT5525, features an on-chip RF input transformer. The LT5525 offers internal 50-(omega) impedance matching at both the RF and the local-oscillator inputs. These inputs can be driven single-ended without external impedance-matching components, thereby facilitating ease of use and reducing costs. The LT5525's IIP3 is 21 dBm at 900 MHz and 17.6 dBm at 1.9 GHz. At 900 MHz, the noise figure is 14 dB and the conversion gain is −2.6 dB. The LT5525 requires only −5-dBm LO drive. In addition, it offers high port-to-port isolation.

Both the LT5525 and LT5526 operate from a single supply voltage ranging from 3.6 V to 5.3 V. Typical operating current is 28 mA. The devices can operate at a supply voltage as low as 3 V with reduced linearity performance. These devices are offered in a 16-pin, 4-×-4-mm surface-mount QFN package. The LT5526 is priced at $3.40 and the LT5525 is $3.80 in 1000-piece quantities. The products are available from stock.

To learn more about these RF mixers, visit www.linear.com.

Santa Clara, California
Manufacturers of products and systems for defense EW/ECM, test equipment, microwave radio, and VSAT need a compact, broadband chip that offers an easy-to-assemble, single power-amplifier solution. Now, they can turn to Celeritek, Inc. It has made available the the CMM0016-BD—a 1-W, GaAs MMIC power amplifier operating in the frequency range of 2.0 to 20.0 GHz.

To extend its commitment to delivering high-quality, reliable products that meet the customers' demands, Celeritek's new power amplifier is available as a bare die. It is manufactured using the company's proven in-house GaAs pHEMT semiconductor technology. Designed for applications operating within the 2.0-to-20.0-GHz frequency range, the device is an ideal solution for transmit, receive, and IF applications. Typical specifications (at 10 GHz) include high performance of 31.0 dBm, P1dB; linear gain of 9.5 dB; and saturated output power of 31.8 dBm. As a benefit to designers, the chip includes integrated on-chip DC blocking. It also is fully matched and directly cascadable with other broadband driver amplifiers to achieve higher gain performance. These features are all included in a compact chip measuring only 2.32 × 1.30 × 0.076 mm.

The absolute maximum ratings for the power amplifier include a drain voltage of 9.0 V (min.)/13.0 V (max.). Its maximum drain current is 750 mA. The continuous power dissipation is 9.5 W. The PA is rated for a maximum input power of 20 dBm.

Celeritek's CMM0016-BD power amplifier is priced at $285.00 in quantities of 100. It is available through Celeritek representatives and distributor Richardson Electronics-Worldwide. The bare die comes in GelPak packages.

A datasheet with complete specifications, performance data, and assembly, die attach, and bonding procedures is available online at www.celeritek.com.

Sunnyvale, California
The Eclipse II family of ultra-low-power FPGAs from QuickLogic Corp. is now available for applications requiring components that operate over the industrial-temperature range. All Eclipse family members are qualified for operation at the extended industrial temperature range (−40° to +100°C device junction temperature).

Many applications require operation over the industrial temperature range. They include ruggedized handheld devices, portable instrumentation and test equipment, and avionics and civil aerospace systems. Along with the benefits of ultra-low power consumption, Eclipse II also provides small-form-factor packaging, instant-on capability, and bulletproof design security from IP theft and reverse engineering. QuickLogic is planning to release a military temperature version of Eclipse II later this year.

QuickLogic's Eclipse II µW family of ultra-low-power FPGAs combines the enhanced features of next-generation FPGA devices with power consumption that is lower than the consumption available with CPLDs. Eclipse II features include densities up to 320,000 system gates, up to 55,000 bits of on-chip dual-port SRAM, and standby currents as low at 14 µA.

For additional information on Eclipse II, go to the QuickLogic web site at www.quicklogic.com.