The need for wireless connectivity in embedded systems is growing. In general, connectivity is becoming widespread as consumers and enterprises alike become accustomed to having continual access to information resources. As a result, information appliances like PDAs are adding capabilities for voice and data transmission. This connectivity allows more traditional embedded systems to report information to a central clearinghouse and obtain information from outside sources. In addition, systems like point-of-sale terminals and surveillance cameras become easier to implement when they offer wireless connectivity.

A wireless approach to connectivity is an essential ingredient for portable embedded systems, which by definition must operate without cables. When cabling is impractical or costs are high, however, wireless also has its benefits for stationary systems. A factory, for instance, may need printers on the production floor in areas where there are no walls along which cables can be run. Wireless connections avoid the need to provide below-the-floor channels for such installations.

Some embedded systems that need wireless connectivity may actually be incompatible with the devices that will provide that connectivity, however. That's because the bus structure of the embedded CPU often does not match the PCI interface found in most wireless-networking chips. Programmable logic can bridge the two buses. But the choices for bridge architecture and logic technology have a significant impact on the design's size, the software-development effort, and battery life.

A legion of choices exists for implementing wireless data connections. Designers can choose from several varieties of Ethernet (802.11), Bluetooth, cellular telephony, ZigBee, and other standards for implementing a wireless link. But bandwidth, software availability, and other considerations favor the use of Ethernet for many embedded-systems designs. Unfortunately, most of the chip sets for implementing the communications protocols and RF links for wireless Ethernet were developed for the personal-computer market. Because of this, many chip sets utilize the PCI bus for their host-processor connection.

Embedded systems, on the other hand, use a wide range of low- and mid-performance processors. Often, these processors don't offer a PCI-bus interface, which is required to interface to the common wireless chip sets. This situation leaves embedded-systems designers with a dilemma: The wireless chip sets that they need can't directly connect to the processors that they want to use. Unfortunately, cost considerations and the existence of legacy software make changing processors an undesirable option. The only alternative is for designers to implement logic that will bridge the CPU interface to the PCI-bus structure. Often, this task is challenging. For one thing, the CPU bus may not have the same bus width as the PCI bus. As a result, the bridge will have to provide data formatting. Furthermore, the PCI bus doesn't allow for the simple memory mapping that's typically used in embedded systems. Rather, the PCI bus requires a complex protocol for the transfer of data. This requirement forces the bridge to provide data buffering along with the protocol logic. The CPU can then perform other tasks during the transfer.

Another constraint on the bridge design comes from power concerns—especially for portable systems. Most embedded designs now use active power management to keep systems cool and extend battery lifetime in portable systems. This approach requires the ability to shut down power to circuit blocks when they're not actively engaged in their function. Yet many embedded systems need connectivity only occasionally, such as when sending periodic reports to a central office. The wireless connection therefore needs a power-down option. Power-down requires shutting down both the wireless chip set and the bus-bridge logic. The bridge design must therefore provide a method for entering a standby or power-down mode.

Typically, cost is yet another constraint on the bridge design. Many embedded systems for the consumer market are under market pressure to minimize cost. Component cost and the costs associated with extra board space are critical elements. As a result, the bridge design needs to be as compact as possible. This implies a single-chip solution rather than discrete logic. Yet development cost also is a major concern in many embedded systems. Most designers simply can't afford to pay the mask charges or even spend the time needed to develop a custom bridge device.

A good solution that complies with all of these constraints is the use of a field-programmable gate array (FPGA) to serve as the bridge device. Typically, FPGA libraries of pre-defined functions include PCI interfaces. As a result, the bridge design is already half done. The flexibility of the FPGA allows developers to adapt the design to a variety of different CPUs. The design can therefore be used in multiple projects with minimal modification. Because the flexibility minimizes development time and eliminates mask charges, the FPGA design also is much more cost effective than a custom IC—especially in small production volumes.

For the designers who are seeking to utilize FPGAs, it's essential that they consider which base technology suits their needs. The FPGA market offers three base technologies: SRAM-based, EEPROM-based, and anti-fuse-based devices. SRAM-based devices use SRAM cells to hold the programmed values. Those values control the switch transistors, which make the logic-circuit connections within the array. Although EEPROM-based devices use the same basic approach, they employ nonvolatile EEPROM cells to hold the programmed values. Anti-fuse-based devices don't have memory cells or switch transistors. Instead, programming an anti-fuse-based device creates permanent logic-circuit connections.

Along with the FPGA base technology, designers need to consider the bridge architecture that they will require. A simple bridge connects the processor to the wireless chip set without other system interactions (FIG. 1). The FPGA's internal memory serves to buffer data passing to the network connection. But the processor must fill and empty the buffers under program control. The bus-mastering bridge includes a memory-controller block that allows the bridge to move data between the system memory and the network connection without processor intervention (FIG. 2).

Designers have many parameters to consider in evaluating the choices for bridge architecture and FPGA technology. System performance, including the network data rate and latency, may be important in some applications. System complexity, which affects the cost and design time required, is another factor. Along with the hardware effort, designers need to consider the impact of their choices on the software-development effort. Finally, the power demands and cost of the final configuration need to be evaluated.

When the embedded system needs the highest networking performance, the bus-master-bridge architecture is the optimum choice. A simple-bridge design has both data-rate and latency issues. It therefore requires the processor's intervention to move data across the bridge. The time required for the CPU to respond to a PCI interrupt and retrieve the data directly adds to the latency of the wireless chip set in communicating over the network. This latency may not pose a problem for data-logging systems, in which communications are intermittent. But it can compromise the effectiveness of systems like point-of-sale kiosks. Such systems may need an interactive audio link between the customer and a remote salesperson.