There appears to be no end to the functionality that can be added to the next-generation mobile phone. This trend is partially driven by network operators. After all, they can realize a higher annual revenue per user by offering handsets with greater functionality. Support for new applications also is critical. End users are eager to try applications like hot-spot Internet access, WLAN for the enterprise, and GNSS (GPS and Galileo) for new "find-a-friend" and E-911 services. Aside from the operator requirements, legislation is affecting this integration trend. Because it is limiting the use of cellular phones in automobiles, Bluetooth will most likely be added for hands-free headsets. Simultaneously, terminal manufacturers are looking to increase market share through the higher feature integration of games, entertainment radio (FM), television (DVB-H), longer battery life, and smaller size.

To support these emerging applications, engineers need to effectively integrate an increasing number of radios and peripheral functionality. New IC design approaches are therefore required. As to how these functions are integrated into cellular phones, the jury is still out. The question that designers need to answer is, "What provides the smallest, most power-efficient and effective solution while still hitting time-to-market objectives?" It's questionable if this goal is best achieved using a single-chip approach to design. In many cases, system-in-package or multichip modules may offer significant advantages.

Single-chip Bluetooth and IEEE 802.11 WLAN radio transceivers have demonstrated the technical and practical feasibility of integrating radio-frequency (RF) and digital circuits onto a single CMOS die. Complete GSM radios, which exclude the power amplifiers, have been developed using CMOS processes. They could conceivably be integrated with the digital circuits into a single-chip transceiver. Yet the decision of whether to integrate the two onto the same die is not as straightforward as it seems.

The designer's choices include flip-chip, system-in-package (SiP), and multichip modules (MCMs). Each option offers a proven approach with reliable assembly techniques—especially for designs that incorporate RF circuitry. Consider the following factors when determining the degree of integration for next-generation cellular chip sets:

• The time-to-market considerations that are associated with the risks of analog and digital integration
• The impact of the operating voltage
• The pure silicon economics of having a single, larger die as opposed to two or more chips with smaller die that use different technologies

Analog, RF, mixed-signal, and digital circuits are shrinking at different rates. Digital circuits, such as logic and memory, broadly follow Moore's law. As the circuits shrink with the square of the feature size, the overall cost per function also decreases. In contrast, the size of RF and mixed-signal blocks is typically determined by on-chip passive components like resistors, capacitors, and inductors. These components don't shrink. As a result, the cost per function of analog and mixed-signal RF circuitry rises when implemented on the state-of-the-art digital processes that feature smaller geometry (FIG. 1).

The most cost-effective approach to designing large circuits may be to use different dedicated process technologies that are optimized for the analog, RF, and digital functions. The number of additional mask steps, which are required to support analog functions, increases the relative cost of the digital functions. It therefore drives up associated costs in yield and test time. Keep in mind that processing ever-finer line widths demands equipment of increasing precision. As a result, the cost of exposure systems also rises. Systems that cost tens of thousands of dollars in the 1960s are now in the tens-of-millions-of-dollars bracket. Inevitably, this cost impacts market opportunities.

The supply voltage's influence also must be taken into account. As digital transistors get smaller and thinner, core supply voltages must decrease in order to avoid breakdown effects. They also must keep power consumption under control. Submicron processes that operate at core voltages of around 5 V are now a dim memory. The transition to 0.5-µm and below reduced core voltages to 3.3 V. Meanwhile, 0.25-µm gates reduced core voltages to as low as 1.8 V.

As the latest digital processes transition to 90-nm or smaller line widths, core supply voltages of 1.0 V or lower can be realized. These lower-voltage devices make it increasingly difficult for designers to create functional analog and mixed-signal RF circuits—especially if they have to interface to the real world. To address this low-voltage issue for the I/O pads of digital chips, designers can add larger-geometry devices with thicker gate oxide (typically from the previous-generation technology). In some cases, this approach will allow mixed-signal circuits to be added. If the area is significant, however, a more cost-effective approach would be to implement these circuits in a larger-geometry process.

Lowering the supply voltage decreases the voltage range that is available to represent analog signals. Thus far, designers have only been able to accommodate analog circuitry during process shrinks by creating new circuit topologies. Such topologies maximize the analog range. It's difficult to envision how this method can be sustained through further scaling of the power supply—particularly for geometries below the 0.13-µm node. If the analog range cannot be increased, designers are left with no alternative but to improve signal-to-noise ratios. Smaller feature sizes will make the device operate faster and at lower voltages. But this improved operation will be at the expense of both current and power consumption.

Shrinking process geometries also make "first-time success" increasingly unlikely. According to September 2003 presentations to Synopsys User Groups, no less than 61% of new application-specific integrated circuits (ASICs) and ICs require at least one re-spin.* This time-to-market problem is getting worse with increasingly complex designs—especially those with analog and digital elements.

Ten years ago, the majority of silicon re-spins were due to simple problems like connectivity errors. Modern design tools have eliminated most of these basic errors. But today's problems are much more insidious than the ones faced in the past. It's estimated that as much as 80% of the problems in a state-of-the-art design arise from a failure to account for some unanticipated physical effect. Such effects include artifacts that couldn't be modeled or anticipated before the design started.