In recent years, wireless communications have grown to encompass applications like remote control, remote sensing, and wireless local-area networks (WLANs). The data rates of such implementations vary from a few hundred to several million bits per second. In addition, their range can be anywhere from a few to several hundred meters. Yet almost all of these wireless applications are the same in that they provide serial, asynchronous digital data formats.

On the analog side, the physical channels are shrouded in background noise. This noise comes from other transmitters and instruments in the surrounding environment. Moreover, some receivers will detect "fake data" when the transmitter is out of range. An example is a receiver that implements FSK modulation schemes. The "fake data" is actually signals with random frequency. These error challenges necessitate a different way to implement a physical-layer Universal Asynchronous Receiver Transmitter (UART) for the wireless communication line.

This article describes the use of an oversampling technique to transfer data from one microcontroller to another via a transceiver module. The module itself requires no data coding. But the wireless nature of the transmissions demands the use of a receiving algorithm. This algorithm separates valid data from undesirable noise. As a result, the data needs to be sent in packets or frames that have a well-defined format.

Each frame should begin with a preamble of 1 to 2 B (for example, "10101010..."). The second field of the frame should contain the start byte, which is an identification that indicates the beginning of a frame. The rest of the frame will follow the start byte. It should consist of 1 B of an address (ID). It will be followed by the frame data (1 to 100 B) and finally 2 B for a checksum. The general structure of the frame is as follows:

The transmission procedure is simple: The interrupt handler in the microcontroller should send the frame, bit by bit, at a constant rate. This constant data stream is known as the communication rate.

The receiver is on the other end of the transmission system. The receiving routine is more complex than its counterpart on the transmitting side. For example, the receiver interrupt handler may be triggered by an edge-level rise or fall. Such triggering might cause the interrupt handler to sample the input stream in the middle of each bit. The result would be a reduced data rate of only one sample per bit. This rate would produce an output that is much more sensitive to noise than the oversampling approach.

When using oversampling, the receiving routine should sample the received bit stream at several times the bit rate. After being acquired, the samples must be weighted according to a weighting table. All of these computations result in a very reliable transmission link. Oversampling at a rate of 10 times the bit rate with sample weighting, for example, will produce a result that is noticeably resistant to noise.

Designers must note, however, that timing is critical because the sampling period must be consistent. If one uses the microcontroller interrupt to implement an oversampling, all of the system resources will be at the mercy of the interrupt handler. A better method would be to have a dedicated chip—using programmable logic—that performs the task of oversampling. This method won't tie up valuable system resources. At the same time, it will enable much higher oversampling rates (e.g., sample rates of tens of megasamples per second).

Consider the use of a hardware-based oversampling UART (FIG. 1). Component U1-CY37064P44 is a programmable-logic device (CPLD) from Cypress Semiconductor (www.cypress.com). This component boasts 64 macro cells. It has 44 pins that are triggered by a 20-MHz clock. Of course, any other CPLD with similar capabilities also could be used. One example might be the ispMACH4A from Lattice Semiconductor (www.latticesemi.com).

The designer can program the CPLD with any industrial, parallel CPLD programmer. But a preferred method is to use In-System Reprogramming (ISR). J1 is a JTAG connector, which is designed for this purpose. The designer connects the UltraISR or C3ISR programming cable between J1 and PC. After loading the appropriate JED file, he or she can then begin programming the device.

In this UART circuit, one serial input (D) receives the bit stream from the transceiver module. A data bus (DATA) transfers a complete byte to the microcontroller. That microcontroller contains the traditional control ports for interrupt request (INTR): trigger the microcontroller, interrupt acknowledge (INTA), and a busy line (BUSY).

The internal architecture of the CPLD can be described using state-machine diagrams (FIG. 2). The state machine includes several constants: PreBits (number of bits in the preamble); StrLen (number of bytes in the frame excluding the preamble); and Tnx (number of samplings per bit). In addition, there are four counters: Ax, Bx, Cx, and Sx. They count bytes, bits, oversampling index, and oversampling data, respectively. The CPLD contains one register (PR) to store the received bits. At IDLE state, the machine is waiting for a rising edge in the input stream D, which is the beginning of the preamble.

The next six states act as a preamble detector. At states S1 and S0, the machine oversamples bits '1' and '0' of the preamble. At states FALL and RISE, the machine checks if the average sample is correct. The machine checks for the end of the preamble at states S2 and S3. The busy line is set at GO, which means that real data is received.

At state S4, the machine oversamples and averages the data bits. At LOAD, eight average data bits are packed into 1 B. An interrupt request (INTR) is sent to the microcontroller at state W0 to collect the byte. At state BYTE, the machine checks for the end of the frame. Finally, at FIN, it clears the busy line to indicate that the entire frame was received. The DAMI state is for balancing the path in the machine. If INTA occurs at any state, the interrupt acknowledge (INTR) will clear.

Several methods are commonly used to design, synthesize, and simulate the content of the complex programmable-logic device. Typically, VHDL code is written according to the state-machine flow to synthesize and simulate the design. In VHDL, the designer can search for the best tradeoffs between the clock frequency, data transfer rate, and number of bytes per frame. For example, the VHDL source file created for this oversampling project was based on a 20-MHz clock, 200-kbps data transfer rate, 12 B per frame, and a preamble of 8 b (SEE SIDEBAR). Naturally, the designer can change those values as necessary to examine other tradeoff conditions.

A testbench is needed to verify the VHDL simulation. Given the preceding example, the simulation would start with high-frequency noise (500 kHz) followed by a correct preamble and 12 B of data (a complete frame). The resulting simulation would help to test the design (FIG. 3).

Here, the testbench indicated that the UART rejects high-frequency noise (or a preamble with a different frequency). The correct preamble is detected and the BUSY line is set. The 12 bytes that follow the preamble (complete frame) are 33, 37, 00, 01, 02, 03, 04, 05, 06, 07, 08, and 09. Although the second byte (37) includes high-frequency noise at the fourth bit, the UART rejects this noise. It sends the corrected data to the bus. One can see that the UART packs eight serial bits to one parallel byte and triggers the microcontroller by the INTR command. When a complete frame is received, the BUSY line turns to zero. The UART is then ready to receive the next frame.

This article presents one way to implement a physical layer (UART) for wireless communications. By using an oversampling technique, designers can follow this very approach. It should lead them to develop a subsystem that is resistant to noise and other interference.