As cellular phones incorporate the multi-function capabilities that enable web-access and digital-camera functionality, their supporting memory subsystems grow increasingly complex. For engineers in today's cell-phone market, one of the main design challenges is to meet the demands for higher density and performance memory. Of course, they must do so at a lower cost and in a smaller space. At the same time, designers must identify a flexible solution to accommodate the need for low-end, mid-range, and high-end configurations.

Major design changes to the overall phone design may not be part of this solution. The cost and performance tradeoffs for different densities and types of memory must be balanced for specific handset designs. This is the only way to optimize the overall memory subsystem so that it best meets these conflicting requirements.

Previous "talk-only" mobile phones utilized 4 to 8 Mb of low-power SRAM for working memory and data storage (phone numbers, call logs, messages, etc.) backed up by button battery. For code storage, they used 16 Mb of NOR Flash or E²PROM. As phones became smaller and feature sets grew, multi-chip packaging (MCP) was developed. In a single package, it combined a 4-Mb SRAM die with an 8- or 16-Mb NOR Flash chip. The result was a reduction in space requirements for cell-phone memory.

In today's rapidly evolving cellular market, however, memory density has increased to support a diverse range of cell-phone applications. Consumers now demand feature-rich phones. These devices perform Internet browsing, text messaging, games, the downloading and playing of music, and digital-camera functionality and applications (including the ability to take, transmit, receive, and display photos). Such applications have caused an increase in the complexity of memory requirements.

Typically, cell-phone manufacturers now use 8 to 16 Mb of low-power SRAM for data backup; 32 to 128 Mb of Pseudo-SRAM (PSRAM) for the working area of the system; and 64 to 128 Mb of NOR Flash for bootable code storage on basic phone programs. They also employ 128 to 256 Mb or more additional memory—often NAND Flash—for application software and the storage of huge data, such as pictures and music (FIG. 1).

Meanwhile, handset size continues to shrink. The space that's available for the memory subsystem is the same or even less than it was previously. Today, multi-chip packages are available to combine a complete, complex memory subsystem in a single, small package. For example, a ball-grid-array (BGA) package with five stacked memory chips can be as small as 9 3 12 3 1.4 mm, depending on the specific memory configuration. Semi-custom combinations of two, three, or four types of memory—with stacks involving up to five or six chips—also are being combined in a single package. Technically, up to nine layers are now available in a stacked MCP product with higher stack variations on the horizon. And MCP uses standard package technology like gold bonding wire, which doesn't require an additional investment for a mass production line.

Memory-capacity requirements are driven by the increasing diversity of applications. For another view of the application and on-board memory trend, examine the combined total RAM plus Flash-memory requirement for various cellular-phone applications. Such applications include e-mail, Internet browsing, Java applications, camera/movie capability, and music playback (FIG. 2). The need for memory to support games, Internet browsing, e-mail, and camera functionality has grown at a much faster rate than was originally anticipated.

Before detailing the mix and density of memory chips for a specific handset design, it's important to consider the basic memory architecture. Two leading alternatives currently exist. The first option is a higher-density, higher-performance version of the conventional NOR+SRAM memory architecture. Often, it uses some combination of NOR+PSRAM+NAND. The other alternative is a newer, lower-cost solution that uses NAND plus low-power SDRAM. This latter option offers interesting performance advantages.

The conventional memory architecture for multi-function cell phones typically uses NOR Flash for code storage, PSRAM for work space, and NAND Flash for data storage. In some markets, SRAM is used for backup (FIG. 3). Designers often build upon the conventional cell-phone memory architecture by increasing the density of the NOR and PSRAM. For data storage, they add NAND Flash because NAND Flash has the lowest cost per bit.

To achieve improved system performance, even memory vendors have begun supporting Burst NOR and Burst PSRAM. The advantage of the Burst architecture is that it doesn't require major software changes. As a result, it helps to shorten development time and testing requirements. Such an architecture supports a reasonable speed while achieving sufficient performance. It also demands relatively low power consumption.

The new lower-cost alternative replaces NOR Flash for code storage with NAND Flash. Using a shadowing architecture, it brings stored code from NAND Flash into SDRAM for working memory (FIG. 4). When it's used with chip sets that support NAND for code storage, low-power SDRAM (with a typical speed of 83 MHz and up) combines with NAND-Flash memory to provide a cost-effective, high-performance solution for cell-phone memory subsystems. In addition to its much smaller cell size, NAND costs significantly less than NOR. Thanks to its significantly faster programming and erase times, it also can provide an overall performance improvement.