Third-generation (3G) wireless access will soon make its way into products like portable game consoles. This evolution will enable users to play interactively with friends anywhere and anytime. Compared to previous-generation wireless systems, however, 3G raises multifold design obstacles. With dynamically changing parameters and closed-loop operation between the transmitter and receiver, 3G modems demand diligence in system design.

To help meet third-generation wireless standards and optimize performance, designers of 3G wireless-handset digital-baseband receivers must plan carefully. They must prepare to deal with the project's complexity and optimization requirements from the beginning. Meeting this goal requires a seamless design and verification flow. This flow must start with a high-level, floating-point representation for algorithm optimization. A refining of the implementation for hardware, software, and their interfaces will follow. By adhering to this methodology and taking advantage of available standards-based models, hardware and software developers can accelerate the design process.

This article describes some of the functions and requirements for a modem that complies with the frequency-division-duplex (FDD) UMTS wideband CDMA (WCDMA) wireless-system standard. This information stems from the work of a design team within Synopsys Professional Services. This group created a UMTS-FDD digital-baseband receiver and transmitter for use in 3G-handset applications. The modem was developed from high-level product requirements. It was implemented as part of a complete 3G-handset prototype that was successfully tested with commercial testers. Speech calls and video transmissions to a UMTS-FDD base station have been conducted successfully.

The modem contains a significant amount of control flow functionality. This characteristic facilitates dynamic Layer 1 (L1) configuration changes, as well as closed-loop operation between base transceiver stations and user equipment. These functions have high computational requirements. In addition, they must support user bit rates as high as 2 Mbps. A significant part of the hardware is thus dedicated to baseband-dataflow signal-processing tasks with a sophisticated interface to the L1 software.

Much of the design information presented here concerns the operation of the random-access channel. Among other things, this channel is used by a handset to initiate connections with a base station. Because this channel involves many of the modem's hardware units and software functions, it provides a good view of 3G design issues. Understanding the workings of this random-access channel requires an overview of the modem's main capabilities.

A frequency-division-duplex modem contains both a transmitter and receiver (FIG. 1). The latter component is by far the more complex of the two parts. It therefore occupies the bulk of this article. Yet it also is useful to have an overview of the transmitter.

Essentially, the transmitter's role is to get the data part of the physical channels to be transmitted as input from the channel encoder. It multiplexes the physical-channel data bits with the physical-channel control bits. It then spreads and scrambles the subsequent data stream. The result is a stream of chips that modulates the transmit filter. In this process, the transmitter must control the associated power amplifier for uplink open-loop or closed-loop power control. If necessary, it also must adjust the transmit timing. Note that part of the finite-state machine, which handles the system's random-access function, also is implemented in the transmitter hardware.

As for the receiver, sampled analog-to-digital-converter (ADC) data enters the digital front end. There, matched filtering takes place. The matched-filter output feeds the cell searcher, multipath searcher, and RAKE receiver.

The cell searcher performs initial cell acquisition and monitoring, including the determination of the appropriate scrambling code and frame timing. Based on the coarse timing provided by the cell searcher, the multipath searcher estimates the power delay profile. The output of both the cell and multipath searchers feed back to the L1 software.

L1 and higher-layer software run on a microprocessor core, which is referred to here as the CPU. The main tasks of the L1 software include evaluating and monitoring the power delay profile as provided by the multipath searcher. The L1 software also assigns RAKE fingers to received echoes. As indicated by higher-layer software, the L1 software dynamically configures RAKE and combiner physical-channel processing. This task includes variable-rate and compressed-mode transmission. Higher-layer software also prompts the L1 software to schedule and initiate measurement tasks.

The RAKE receiver comprises the following: RAKE fingers, global blocks, an automatic frequency control (AFC), a combiner, and a unit that generates power-control signal-to-interference ratio (SIR) estimates (FIG. 2). The RAKE-receiver fingers perform physical-channel demodulation. This process includes functions such as time tracking, frequency-offset estimation, channel estimation, and diversity decoding. The combiner performs time alignment (elastic buffering) and maximum ratio combining of the finger output symbol streams. The combiner output goes to the traffic channel decoder.