The term "software-defined radio" refers to the use of software-programmable hardware to provide flexible radio solutions. It is conventionally abbreviated as SDR (see sidebar). The concept behind the technology is that it will provide software control of radio functionality. Traditional radio designs are constructed of fixed analog or digital components. Such designs also are custom built for each application. By comparison, SDRs offer an inherent flexibility. It serves as the main incentive to engage in an SDR methodology. It also makes it possible for an SDR approach to be applied to many radio-based applications.

Fundamentally, software defines the radio functionality. The use of a uniform hardware platform is therefore possible across multiple applications. To transform radio function and operation, SDRs also allow on-the-fly dynamic hardware reprogrammability. With a layered software structure and the adoption of hardware and software industry standards, it is possible to provide varying degrees of abstraction from the underlying hardware. This simplifies porting of the software to future hardware—a feature of particular importance to the defense industry, where systems often require multiple upgrades. The system lifecycle may exceed the availability and capability of hardware technologies.

Currently, SDR embraces a varied scope of radio applications. It is becoming increasingly evident that it can be applied to systems that differ in the number of antennae, channels, and processors. For example, a high-performance direction-finding system may have eight receiving antennae, while requiring 64 digital downconversion (DDC) channels and 40 processors. A tactical military radio, on the other hand, may only require two processors and one each of the antenna, DDC channel, and digital upconversion (DUC) channel. To facilitate the use of a uniform software/hardware approach, it is therefore critical that both the hardware and software can be easily scaled with minimal limitations. This is especially true for the data interconnects between the processing devices. Toward that end, this article examines issues, available technologies, and solutions for typical SDR processing systems.

Thanks to the emergence of SDR, commercial-off-the-shelf (COTS) systems structured on standard backplanes, FPGAs, and processors have become a cost-effective implementation. With the reprogrammability of the SDR, it is no longer necessary to discard the entire system hardware as the system evolves technologically. System re-engineering is a more software-oriented task. In practice, however, it is likely that certain elements of the hardware (e.g., ADCs and DACs) will need to be replaced and upgraded to meet improved system specifications.

To ensure the disposal of the minimum amount of hardware at a system upgrade, the system must be constructed in both a modular and scalable fashion. In this way, only the necessary elements will require upgrading. This modularity and scalability also make the hardware applicable to a wider range of radio applications. In practice, this means a scalable data-interconnect mechanism is important. If the interconnects support a standard data-transfer protocol like TCP/IP, software porting to a new platform will be easier. Of course, the new hardware must support the same protocol.

New solutions have been developed to address the issue of SDR processing systems. One such solution hails from Spectrum Signal Processing. Known as the Solano Communications IC, this chip connects devices in a system by providing point-to-point data channels between the devices via low-voltage differential signaling (LVDS). It provides a total of four such dedicated data links, called quicComm links. Each of these links is capable of up to 200-Mbps full-duplex communication. The chip also has an internal direct-memory-access (DMA) engine to relieve the processor of the data-movement operation.

Solano provides each device with routable, high-speed, low-latency data paths to other system devices. It interfaces to each quicComm link as a simple memory location (FIFO). The chip can be used with processors, as well as with FPGAs, ADCs, and DACs with minimal, if any, interface logic. As a result, the processing heart of the radio system can be constructed with a common interconnect fabric. This possibility simplifies the overall system software by enabling the employment of a uniform software library. And it offers the potential to build heterogeneous processing architectures. Just use different processors, making sure that each one has a Solano interface.

A modular approach to SDR system construction can further build upon the 'point-to-point' data-link concept. The links can be routed off modules using extra connectors. They could even be routed off of a PMC by a connector that still complies with the PMC specification. This approach offers the enhanced capability to support direct data links to the module motherboard. It also provides an alternative data path to the standard PCI bus interface. The enhanced PMC or ePMC module forms a flexible and scalable modular concept on which to design and construct systems.

An example of such a modular concept is illustrated in Spectrum's range of VME-based flexComm HCDR systems. These systems provide an ideal architecture for wireless applications. The system is assembled using carrier cards that support ePMC modules. The carrier card exists as either a single- (PRO-1900) or dual-slot (PRO-1900 and PRO-1901) VME64x board. It offers easily scalable modular I/O and processing by supporting up to five module sites. Four of these sites are interconnected with quicComm links, which are also available at the VME front panel and P0 backplane connector.