Third-generation (3G) base-station designers are facing tough design choices. They must keep up with increasing performance requirements while reducing system power dissipation. At lower power, a hundredfold increase in performance can be achieved. To attain it, use advanced process technology and partition the design into arrays of small, optimized data-processing functions. This distributed-processing approach increases 3G-system efficiency. After all, large arrays of small function-specific processing elements are inherently more efficient than the alternative—small arrays of large, do-everything processors.

For arrays of 3G function blocks to work in parallel, however, they must be connected with a dedicated system-level interconnect structure. It is possible to manage the system data flow using traditional methods like buses, crossbars, or tunnels. Beyond a small number of processing elements, though, data-transfer determinism is lost. The whole system may then unglue. Corner cases and unpredictable latencies are known to cause this problem.

3G designers are now turning to two-dimensional (2D) connectivity fabrics to meet the hundredfold performance increase at lower power. Such fabrics efficiently link arrays of data-processing elements. Their uniform and deterministic structures spread the data traffic over the entire design area to eliminate signal-routing congestion and data-transfer bottlenecks.

With data processing distributed in two dimensions, designers can more easily partition a 3G design. This partitioning can be done to achieve the right balance of size. Or, it may help to determine the number of data-processing components required to keep the chip circuitry busy most of the time. At the same time, partitioning will reduce the overall distance that data has to travel inside the ICs.

CONNECTING SUBSYSTEMS
With billions of transistors switching at gigahertz frequencies, the problem of getting signals across a large die is becoming very complex. Timing, signal integrity, and power issues all have escalated to a new level. Figure 1 shows that instead of spanning the entire chip, 3G functions will have to be localized in small computing platforms. These platforms will be tuned to specific classes of tasks. To work in parallel, these computing islands will have to be bridged with an efficient data-communications structure.

Traditional interconnect methods, such as buses, crossbars, and linear tunnels, are all based on one-dimensional (1D) I/O structures. These structures can directly connect only a limited number of subsystems. In addition, they cannot provide any control over the data-transfer direction. Using these traditional I/O methods to connect large arrays of computing elements also introduces additional glue-logic components and long, non-uniform data routing paths.

For small designs, Figure 2 shows that those traditional I/O methods have worked. They become increasingly inefficient, however, for high-density systems operating at gigahertz clock rates. Finely tuned subsystems can be easily thrown out of tune if they are connected at the system level with a non-uniform mix of traditional I/O methods.

It is better to connect 2D arrays of data-processing elements with a uniform array of 2D data-transfer links. Such connectivity uses a uniform array of short point-to-point routing links. Plus, it requires no additional glue logic. One example of a 2D-fabric I/O structure comes from a company known as CrossBow Technologies. To efficiently connect arrays of subsystems, this company uses a uniform array of horizontal and vertical transport links. Subsystems can then talk to other subsystems through I/O wrappers, which are placed around connected subsystems. Each wrapper is assigned a unique set of YX coordinates. These coordinates are used to route data packets around the system.

On the inside, each 2D-fabric wrapper is accessed with conventional bus cycles—just like any other peripheral. On the outside, though, the adjacent wrappers are connected on all four sides with data transport links. This approach forms a deterministic system-level communications structure. It is uniform in two dimensions.

In Figure 3, a 2D-fabric structure is linking 12 data-processing subsystems inside a single IC. All connected subsystems are wrapped with 2D-fabric wrappers. To each subsystem, they appear as a conventional peripheral on the local bus. Adjacent wrappers are connected with an array of short horizontal and vertical data-transport links. These links enable the transfer of data between subsystems.

Figure 4 shows the write, transport, and read stages of a single data transfer between two subsystems. To launch and receive packets, the source and destination subsystems use conventional bus cycles. All system-level routing and arbitration is performed autonomously by 2D-fabric peripherals along the transfer path.

The source subsystem, which has 2D-fabric YX coordinates of 24h, sends data to subsystem 31h by issuing a write cycle. The local 2D-fabric peripheral converts the write cycle to a single packet. The payload consists of 4 B from the data bus and an optional control byte from the address bus. The packet header, which also is derived from the address bus, contains the YX coordinates of the destination subsystem that is equal to 31h.

The exit direction field of the address bus does not become a part of the packet. Instead, it is used to launch the packet in one of four possible directions (in this case, west). Following the launch, the packet is autonomously routed by three intermediate 2D-fabric wrappers (23h, 22h, and 21h) to arrive at the destination subsystem, 31h. Here, it is received with a read bus cycle.