Today's mobile wireless devices demand power-efficient systems. At the register transfer level (RTL), however, it is very difficult to accurately estimate power consumption and design for low power. The problem is that power usage depends on the actual circuit structure. The goal of Atrenta's RTL predictive analysis toolset, known as SpyGlass Low Power, is to simplify this task. By enabling users to create power-efficient RTL early in the design cycle, Atrenta claims to significantly reduce power design iterations.

Using a unique predictive analysis technique, SpyGlass can perform detailed structural analysis on Verilog and VHDL RTL. This capability greatly aids the detection of complex design problems early in the design cycle. The results are reduced development costs, lower risk, and early time to market. By having the RTL designed for low power, engineers also can get better results with downstream power-optimization tools. Furthermore, SpyGlass Low Power promises that its built-in knowledge base of low-power design techniques can make almost any engineer into a low-power-design expert.

Atrenta, 2001 Gateway Pl.
Suite 440W, San Jose, CA 95110; (408) 453-3333, www.atrenta.com.