One of Cadence's big announcements at DAC concerned a new auto-wirebond capability for designing stacked-die packages. For space-constrained cell phones and wireless handheld devices, reduced chip-size advantages can be gained from stacking die two, three, and four high. Unfortunately, successfully designing a stacked-die package has not been an easy task. Most stacked-die packages use wirebonding for electrical interconnect. For a package designer, this results in hundreds of wires in a stack and greatly increased complexity.

To address this complexity, the new Cadence Auto Wirebond capability automates the design process for stacked die. It includes features to reduce time-consuming iterations and ensure product reliability. Automated wirebonding capabilities are now integrated into the Cadence Advanced Package Design (APD) Suite—an environment for the rules-based physical design of complex, high-density packages. Other features include the ability to bond as many die as desired; use different spacing rules for each die and quadrant; and create multiple bonding patterns so that one substrate can handle multiple-die combinations. The Advanced Package Designer also provides the capability to combine flip-chip and wirebond die in the same design.

This stacked-die automated-wirebonding capability is part of the Advanced Package Designer version 15.0. For a one-year license, it starts at a U.S. list price of $27,000. It is supported on the Solaris, HP UX, and IBM AIX platforms as well as Windows NT and 2000.

Cadence Design Systems, Inc.
555 River Oaks Parkway, San Jose, CA 95134; (800) 746-6223, www.cadence.com.