Smart phones, personal digital assistants (PDAs), and other devices are luring users with increased functionality and personalization options. These designs are based on standard operating systems. They have PC-like functionality and an operational look and feel. The new devices support multiple software applications and more sophisticated hardware, such as color screens. With a greatly increased area, they can store a mix of audio, video, and text files. To incorporate such impressive features, however, their storage requirements have had to become substantially greater. For example, 2.5G handsets incorporate 128-Mb (16-MB) or even 256-Mb (32-MB) Flash memory. In contrast, 2G handsets housed only 16 to 32 Mb (2 to 4 MB) of memory.

As storage requirements continue to climb, the demand for sleek packaging also must be met. This is particularly true for the smart-phone market, in which small size and low weight are critical design elements. To gain competitive ground, Flash-memory vendors are trying to squeeze more and more capacity into constantly shrinking silicon dies. Only a handful of technologies have found a way to pack more information into a single memory cell. Of these technologies, multi-level cell (MLC) is considered the most mature.

By reducing Flash die size, MLC technology achieves a breakthrough cost structure. Using binary or single-level-cell Flash technology, it stores two or more bits of data per physical cell instead of the traditional one bit per cell. MLC does face some obstacles, however. The increased density of the MLC-based Flash media affects data reliability and performance. In addition, MLC must program and sense the correct voltage level accurately and quickly.

Various hardware and software solutions on today's market vow to overcome these problems. Their goal is to enable MLC technology for NAND, NOR, and AND Flash media. No single company has managed to live up to this task on its own. Through partnerships, however, a few companies have introduced products that implement MLC technology with varying levels of success: Intel with NOR Flash, Hitachi with AND Flash, and Toshiba with NAND Flash. MLC Flash was first mass-produced by Intel in 1999, known by the name StrataFlash. This product doubles the capacity of NOR Flash while achieving adequate reliability. Unfortunately, its performance is far slower than standard NOR Flash.

Compared to NOR and AND devices, NAND Flash appeared to be the ideal media for data storage. It flaunts high-speed erase and write, high density, and small size. Based on these characteristics, Toshiba chose NAND Flash as the basis upon which it would implement MLC technology. The company's first MLC NAND product was introduced in December 2002. It offers up to a 50% decrease in die size compared to standard NAND. When matched against competing NOR MLC products, it claims to decrease size by about 70%.

NAND Flash itself is not a perfect media, however. It contains a number of randomly scattered bad blocks. It also requires on-the-fly error correction. Because it uses a non-standard I/O interface, it is difficult to integrate. These limitations are dramatically worsened in MLC NAND. Some other problems are also exacerbated. These include the different software interfaces and a slower programming time compared to standard NAND. The combination of these characteristics makes MLC NAND extremely difficult to use as a standalone local-data-storage solution.

Figure 1 shows the basic structure of a Flash memory cell. Though it is similar to a standard MOS transistor, a Flash cell must be able to retain its charge after power removal. Only then can it permanently store data. To enable this charge retention, a layer called the floating gate is added between the substrate and the select gate. Layers of oxide isolate it from the substrate and the select gate.

A transistor can be biased to optionally conduct a current between its source and drain. In other words, voltage can be applied to the source, drain, gate, and substrate. The voltage level at which the transistor conducts is called its threshold voltage (V_Th). The transistor only conducts if the voltage between the select gate and the source (V_GS) is larger than V_Th. Adding/removing charge to/from the floating gate modifies V_Th.

To determine if the floating gate is charged, two conditions must be met. A specific V_GS must be applied to the cell. In addition, the circuit must be capable of sensing if the transistor is conducting. These basic elements are needed to implement Flash data storage.

In Flash devices that implement binary-Flash technology, two possible ranges exist for V_Th. In contrast, MLC technology can have several valid V_Th ranges. The first implementation of MLC uses four voltage levels (FIG. 2). Each state is mapped to one of four combinations of two bits. As a result, the cell can store two bits of data.

Figure 3 shows some of the complexity that is spawned by the migration from binary Flash to MLC. Because the circuits must maintain tighter V_Th tolerances, the programming and erase processes become more complicated. The result is longer program and erase times and a more complicated read process.

MLC also offers financial benefits. Its high-density design innovations reduce silicon die size, which is the major contributor to overall device cost. For MLC NAND, this reduction in size and cost is greatest in capacities of 256 Mb (32 MB) and higher. That die can be up to 50% smaller than dies that provide a same-capacity binary-Flash device. This savings must be measured in both dollars and space.