The increased use of portable, wireless, battery-powered electronic systems is driving the demand for integrated-circuit (IC) and system-on-a-chip (SoC) devices. After all, these devices consume the smallest possible amounts of power. With every new product generation, users demand smaller size, increased functionality, and longer battery life. In the case of a modern cell phone, for example, users expect advanced features. They think that the phone should have the ability to act as a personal organizer, play games, take and transmit pictures, connect to the Internet, and so forth. At the same time, they expect the device to weigh in at around 4 oz. or less. The device's battery is expected to last at least three hours when in use, or five or more days while in standby mode.

Whenever the industry moves from one technology node to another, existing design constraints are tightened. New constraints then emerge. In the case of today's increasingly complex and sophisticated devices, power, signal-integrity (SI), and timing constraints need to be imposed throughout the entire design flow. Such an approach should maximize the quality of results as well as the reliability of devices.

The problem is that power considerations, SI issues, and timing effects are related. These relationships become more significant with deep-submicron (DSM) implementation technologies. The combination of design power closure, circuit power integrity, signal integrity, and timing closure are a major drain on engineering resources. They impact the device's total time to market.

To create optimal low-power design, tradeoffs like timing versus power and area versus power must often be made at different stages of the design flow. At the same time, the timing and integrity of signals must be ensured. Engineers therefore need access to appropriate power, SI, and timing-analysis and optimization engines. Such engines need to be integrated with, and applied throughout, the entire RTL-to-GDSII flow.

Furthermore, the complex interrelationships between diverse effects must be handled. It is necessary to use an integrated design environment in which all of the power, SI, and timing tools are fully integrated with each other. The flow also should have other analysis and implementation engines. For example, varying cell sizes affect their associated currents (and power consumption). This, in turn, affects the voltage drops associated with these cells.

To fully account for the impact of voltage-drop effects, it is important to derate for timing on a cell-by-cell basis based on actual voltage drops. The timing-analysis engine should concurrently make use of this derated timing data to identify potential changes to the critical paths. In turn, the optimization engine should make appropriate cell sizing changes to address potential setup or hold problems, which appear as a result of the timing changes. This will affect the currents, which will then affect the voltage drops, and so on.

Similarly, voltage drops can alter the noise margins and the susceptibility to crosstalk effects that are associated with a cell. These crosstalk effects impact cell performance in terms of functionality and timing. To fix timing, it may be necessary to resize the cells. Resizing, in turn, affects their power consumption and associated voltage-drop effects. These effects impact their noise margins and susceptibility to crosstalk, and so on. If any of these interrelationships are not addressed due to the lack of a concurrent, integrated design environment, the competitors will surely be first to market with lower-power designs.

The term quality of results (QoR) refers to the way in which engineers measure different aspects of a design compared to the original design goals. They assume that the higher the speed, the higher the quality; the smaller the die size, the higher the quality; the lower the power dissipation, the higher the quality, etc. This article shows how concurrent analysis and optimization delivers lower-power designs with higher QoR. An introduction of the key signal-integrity, power-dissipation, and power-distribution considerations follows:

Common signal-integrity effects
Early IC implementation technologies were cell-delay dominated. The delays associated with the logic elements far outweighed the delays associated with the interconnect. By comparison, today's DSM implementation technologies are interconnect-delay dominated. In terms of relative magnitude and significance, resistive and capacitive (RC) interconnect-delay effects that used to be third or fourth order are now first order. As a result, any changes in signal behavior can have a major effect on the design's quality.

Increased sidewall-capacitive coupling
Again, look to early IC implementation technologies. The aspect ratio of tracks was such that their width was significantly greater than their height (FIG. 1A). Feature sizes continue to shrink, however. The processes that were used to create these devices result in track aspect ratios in which height predominates over width (FIG. 1B).

The outcome is a dramatic increase in the coupling capacitance (C_XCOUP) between the sidewalls of adjacent tracks relative to the substrate capacitances, C_AREA (track base to substrate) and C_FRINGE (sidewall to substrate). Also, today's devices are associated with high integration densities. They can support eight-plus metallization layers. Yet these integration densities result in significant capacitive coupling between adjacent layers, as represented by C_CROSSOVER (FIG. 2). The combination of these factors leads to a tremendous increase in the complexity of crosstalk-related noise (glitch) and timing effects.

Crosstalk-induced glitches
When signals in neighboring wires transition between logic values, the coupling capacitance between the wires causes a transfer of charge. There can be significant crosstalk-induced glitches, depending on the slew of the signals (the speed of switching in terms of rise and fall times). These glitches also are impacted by the amount of mutual crosstalk capacitance or C_XTALK (Figure 3).