Cell Phones Demand Better Battery Life

Just a few short years ago, the expectations of cell-phone users centered around one capability: being able to reliably conduct voice calls while they were away from a wired telephone set. Since then, impressive technological advances have been achieved. The brick-sized, transportable phone sets of yesteryear have morphed into soon-to-be-available, 6+-megapixel camera phones. Such devices offer DVD-quality video and a high-fidelity music player. They also flaunt a high-end, 3D-graphic gaming console and high-speed wireless-Internet-connection combinations.

To put it simply, cellular phones have stopped being just telephones. These "Swiss army knives" of the personal communications system are now the most impressive example of the convergence of computing, communications, and personal entertainment. With these devices, one can generate, share, enjoy, and store multimedia information as part of today's on-the-move lifestyle.

For the microelectronics industry, however, these supercomputing organisms invite a complex problem: Keeping these products running on very small batteries for longer periods of time is a major challenge. As a result, special emphasis is now being dedicated to extending the battery life of such systems. Designers are expanding their operating time from a few minutes to many hours while standby times rise from hours to weeks.

In doing so, designers are stressing a multi-level matrix of theoretical and practical limits—from the fundamental laws of physics to system-level-optimization techniques. These techniques cannot be added to an existing system later on. They are major components of both application hardware and software. For optimal results, designers must therefore make use of energy-reduction-enabled, foundation-semiconductor structures. Such structures include logic elements, input/output cells, and memory blocks. At the same time, designers must implement dynamic power-consumption-management procedures.

This article will explore some of the most advanced system-level energy-management techniques that are currently in development. It also will analyze how these techniques are enabled at the foundation-semiconductor-structure level. A quantitative estimate of the resulting battery-life extension will then be calculated for a system. This estimate will make smart usage of all of the techniques that are now available in a commercially available, semiconductor Intellectual-Property (IP) product.

To better visualize the power-management problem faced by a next-generation cell-phone designer, consider the high-level block diagram shown in FIGURE 1. For a device of such complexity, the only strategies that will effectively optimize energy consumption must include run-time-behavior analysis. Such analysis translates into a continuous monitoring of all of the requested services and performance levels at every individual block of the system. It selectively turns off or adjusts the performance of those system elements.

Some of the early, pioneering energy-management schemes simply turned selected areas of a system on and off. These schemes were based on rudimentary utilization algorithms. It's now understood that an energy-waste cost is associated with turning off and on a section of an electronic device. Depending on how frequently a block is turned off and on, this cost may exceed the benefit of powering it off in the first place.

In addition, designers now know that smoothing the discharge profile over time—rather than having dramatic discharge-rate changes—results in longer times between battery recharging. A meaningful run-time-behavior analysis has to consider many aspects, including block workloads, energy-consumption rates, the usage environment, and requested services. Based on a block-workload analysis, adaptive-predictive shutdown techniques can put inactive system areas in power- or shut-down mode. This step occurs as a result of previous usage patterns.

Among the examples of energy-consumption-based power-management techniques are communication-based power management (CBPM) and heat management with passive cooling. CBPM exercises dynamic and proactive control over system components. It delays components that are executing less performance-critical operations even if they're not idle. By dynamically blocking the execution of certain components, CBPM can regulate the system's power profile. In contrast, heat management with passive-cooling procedures monitors the system's temperature. It limits the power consumption of certain sections and even disables services if necessary.

Based on the usage environment, some of the system parameters are adjusted. Such adjustments include compulsory system shutdown. The usage environment could be, for example, the strength of the received RF signal, the intensity of the ambient light, or the remaining battery charge. To reduce battery discharging, some services also may be disabled. Even if the user requests those services, they won't be performed.

As mentioned previously, implementing a comprehensive energy-management strategy imposes new system-level requirements with both hardware and software implications. The software component of such a strategy contributes to its flexibility and adaptability. The hardware aspect includes additional functions and blocks like timers, sensors, and power and clock controllers. It also incorporates very specific transistor-level features, which enable battery-life optimization. Among these system-level requirements are the following:

Multiple power/performance points: All subsystems are able to operate at more than one power-performance level. Estimates indicate that this capability would result in a potential power savings that ranges from 20% to 60%.

Power islands: These independent subsystems are responsible for a meaningful fraction of the system power consumption (around 10%). Each subsystem operates at its own voltage levels and clock frequencies, thereby enabling dynamic power management. The power-reduction impacts are estimated to be in the range of 5% to 40%.

Thermal islands: These independent subsystems are responsible for a meaningful fraction of the system heat generation (around 10%). Each subsystem operates its own thermal level (with sensor and power-level control). Power-reduction ranges depend heavily on specific implementations.

Resource scheduler: This software and hardware structure handles CBPM techniques. System-level silicon-area penalties are estimated to be around 5%. Power-consumption-reduction estimates are heavily dependent on the specifics of each implementation. Technical literature cites extreme examples of a 3X improvement in battery life being achieved.

Sensors for environment context: These sensors monitor aspects like system and ambient temperature, ambient light, battery-charge levels, and user movement. Estimates indicate that this capability would result in a potential power savings of around 10%.

Fine-grain idleness control: These software and hardware structures enable the idleness control of granular system components. This control is invisible to the user. It might include, for example, drowsy caches and processor cores like ARM's ARM1176 IEM-enabled RISC core.

Although cost isn't included in this article's analysis, a smart system designer will select the optimal mix in order to achieve the best cost/battery-life combination for the intended cellular-phone device. By carefully selecting the basic elements that will be used in a design, the designer can keep cost within budget while implementing a wide range of energy-management techniques. The semiconductor components that are included in a cellular-phone design are responsible for a major share of the power that's dissipated. Aside from being developed with features that must support system-level energy-management techniques, these components must also be inherently low-power-consuming structures.

Most of the semiconductor devices that are used in systems like wireless cellular phones are fabricated in CMOS processes. The power that's dissipated by CMOS structures is composed of two factors: dynamic and static power dissipation. Dynamic power dissipation results from the active switching of the transistors' logic state. In contrast, static power dissipation occurs because of the current that leaks from the transistors while they're powered.

The main contributors to the dynamic power dissipation of CMOS structures are the applied voltage, operating frequency, and switching-structure capacitance. For static power dissipation, the main contributors are the applied voltage and the threshold voltage (Vt) of the used transistors. Of course, the silicon manufacturing process also has a huge influence on the overall power that is dissipated.

Recently, numerous innovative power-dissipation-reduction techniques have been used in semiconductor devices. Some of these are listed below:

Dynamic voltage scaling (DVS): The dynamic power that's dissipated by a semiconductor device is proportional to the square of the applied power-supply voltage. DVS techniques are therefore a very effective way of reducing that dynamic power. These techniques consist of applying the lowest voltage to a circuit just enough for it to perform the required system tasks. Dynamically adjusting the applied voltage to the semiconductor device optimizes its power consumption to the required workload. This step is fundamental to extending battery life in deeply embedded systems like today's cell phones. Keep in mind that the effective use of DVS techniques requires an intelligent power supply that's controlled by monitoring-activity software and hardware components. Normally, these techniques are used in conjunction with dynamic frequency scaling (DFS).

Dynamic frequency scaling: The dynamic power that's dissipated by a semiconductor device is proportional to the frequency of the clock signal that's applied to it. It would be inefficient to run a device like a cell phone (which has a required workload that varies immensely over time) at the fixed clock frequency that's needed for performing the highest supported workload. To optimize the power dissipation of the overall system, just adjust the clock frequency that's applied to a device to satisfy the application service's deadlines. Once again, software- and hardware-based intelligent clock controllers are required for applying effective DFS techniques. If the voltage and frequency-dynamic-scaling (DVFS) techniques are combined, the system will operate at the minimal supply voltage and clock frequency that are needed to perform the required services. This approach is one of the most effective strategies for optimizing active, dynamic power dissipation.

Power-island support: When DVFS techniques are applied to subsystems, they create islands within the running system with their own clock and supply-voltage combinations. These subsystems are optimized to the specific workload for that section of the product. A more complex and intelligent power- and clock-controller block is now required. A power-consumption cost exists for getting in and out of a clock/supply-voltage combination. To guarantee an optimal power-consumption profile, the system must be carefully partitioned into power islands in the early phases of development.

Multiple-voltage-threshold (Vt) CMOS: The leakage power of a CMOS circuit comes from several sources. One of the main sources is sub-threshold leakage current, which exponentially increases with the reduction of the CMOS transistors' threshold voltage (Vt). Similarly, the performance of the CMOS transistors increases with the reduction of their Vt. Multiple-threshold CMOS circuits, which combine both high- and low-threshold transistors in a single chip, are used to handle the leakage-power-dissipation problem in battery-operated but high-performance applications like feature-rich cellular phones. Several techniques have been applied, including dual-threshold CMOS and adaptive body biasing (ABB).

Dual-threshold CMOS: When a system's logic partitioning is being implemented, high-Vt transistors are used in non-critical paths. They reduce leakage power dissipation. In contrast, low-Vt transistors are used to handle the performance level that's required in critical paths. This technique is effective for reducing leakage during both active and standby modes.

Adaptive body biasing (ABB): To achieve variable threshold voltages for a system's logic portion, this technique biases the device substrates. In standby mode, adaptive-reverse body bias is applied to increase the device's threshold voltage while reducing leakage current. In active mode, no bias or forward biasing is applied to handle the required performance levels. ABB techniques are a more effective way of reducing the leakage current when compared to DVS techniques. After all, they reduce leakage exponentially rather than linearly (as DVS does).

Deep-sleep modes with logic-state retention: These techniques are used to selectively power down certain regions of a logic block within a system. At the same time, the ABB and DVS techniques are applied to other regions for logic-state retention. These techniques are applied to basic logic elements as sequential logic cells (flip-flops and registers) and memory blocks. They provide very effective power-dissipation-reduction results. At the same time, they save processing energy and silicon real estate when compared to traditional, software-based, state-saving procedures.

Cellular-phone users probably have some of the most demanding expectations out of the whole consumer market. These users want to receive and make voice calls; send messages; take, send and receive photos and videos; listen to music; and play games for extended periods of time before recharging their batteries. For these reasons, cellular-phone developers need to implement every possible and available energy-reduction technique into their designs.